Regviz

Espressif Systems /ESP32-P4 /LP_ADC /READER1_CTRL

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as READER1_CTRL

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Espressif Systems/ESP32-P4/LP_ADC/READER1_CTRL#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SAR1_CLK_DIV0 (SAR1_CLK_GATED)SAR1_CLK_GATED 0SAR1_SAMPLE_NUM0 (SAR1_DATA_INV)SAR1_DATA_INV 0 (SAR1_INT_EN)SAR1_INT_EN 0SAR1_EN_PAD_FORCE_ENABLE

Description

Control the read operation of ADC1.

Fields

SAR1_CLK_DIV

Clock divider.
SAR1_CLK_GATED

N/A
SAR1_SAMPLE_NUM

N/A
SAR1_DATA_INV

Invert SAR ADC1 data.
SAR1_INT_EN

Enable saradc1 to send out interrupt.
SAR1_EN_PAD_FORCE_ENABLE

Force enable adc en_pad to analog circuit 2’b11: force enable .

Links

()

Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data